The present invention relates to a nonvolatile semiconductor memory, a control method of the nonvolatile semiconductor memory, a nonvolatile semiconductor memory system, and a memory card.
In the past, as a nonvolatile semiconductor memory device that is electrically rewritable and has a high integration density, a NAND-type flash memory is known. In the NAND-type flash memory, a NAND cell unit is constructed by a plurality of adjacent memory cells that are serially connected to each other in a form that source and drain regions are shared by the adjacent memory cells. Both ends of the NAND cell unit are connected to a bit line and a source line, respectively, via a select gate transistor.
The memory cell of the NAND-type flash memory includes a floating gate electrode formed on a semiconductor substrate via a tunnel insulating film, and a control gate electrode stacked on the floating gate electrode via an inter-gate insulating film, and stores data in a nonvolatile manner using the change of a threshold voltage based on the amount of charges accumulated on the floating gate electrode. Specifically, a high state of the threshold voltage in which electrons are injected to the floating gate electrode corresponds to data “0”, and a low state of the threshold voltage in which electrons are discharged from the floating gate electrode corresponds to data “1”, whereby two-value data can be stored for each state of the threshold voltage. In recent years, a technique has been developed to store multi-value data (having four values, for example) by subdividing the threshold voltage.
However, with the subdivision of the threshold voltage and with the decrease in the size of the memory cell, data is erroneously programmed, particularly, to the memory cell transistors adjacent to the select gate transistor. Thus, there was a problem that the reliability of the NAND-type flash memory decreases. To solve such a problem, a method has been proposed in which a dummy cell transistor that is not used to store data is provided next to the select gate transistor, which, however, was insufficient to prevent the decrease of reliability (see JP-A-2006-186359, for example).